1st lesson belanja
Maxwell
- Rate RM123
- Response 1h
RM123/h
Contact
1st lesson belanja
- Computer programming
- C
- C++
FPGA, RTL, Operating Systems & Digital Logic Tutor | UIUC Computer Engineering | AMD FPGA Design Engineer
- Computer programming
- C
- C++
Lesson location
About Maxwell
I'm a UIUC Computer Engineering grad and an FPGA Engineer at AMD. I write RTL and debug real hardware for a living.
I tutor digital logic, FPGA design, Verilog/SystemVerilog, Operating Systems, and C, from intro logic courses through senior RTL projects and Vivado bring-up. I also do hardware / Systems interview prep, since I've been on both sides of those screens.
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About the lesson
- Primary
- Secondary
- SPM
- +10
levels :
Primary
Secondary
SPM
Form 6
STPM
Adult education
Masters
Doctorate
Beginner
Intermediate
Advanced
Professional
Kids
- English
All languages in which the lesson is available :
English
First session: you tell me the course, the deadline, and the specific thing that's broken. I look at your code or problem set, find where the understanding actually breaks down, and we start there instead of at chapter one.
Typical session structure:
-Concept behind the problem, with a diagram or waveform, not a definition.
-Working your real assignment, you driving, me asking questions.
-Discuss what to try on your own before we meet again.
For FPGA and RTL work I push simulation and waveform reading early, because reading a waveform is the skill that makes every later bug solvable. For digital logic I focus on state machines and timing, which is where most of the exam points live. For interview prep we do timed whiteboard-style problems and then review what the interviewer was listening for.
I give homework-sized practice between sessions when it helps, and I'm happy to answer short questions by message in between.
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Rates
Rate
- RM123
Pack rates
- 5h: RM490
- 10h: RM858
free lessons
This first lesson is free to allow you to get to know your teacher so that they can best meet your needs.
- 1hr
online
- RM123/h
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