1st lesson belanja
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Sujeet
- Rate RM84
- Response 2h
-
Students6
Number of students accompanied by Sujeet since their arrival at Superprof
Number of students accompanied by Sujeet since their arrival at Superprof
RM84/h
Contact
1st lesson belanja
- Engineering
- Electrical Engineering
- Electronics
- Technology
- Robotics
I have more than 15 years of teaching and solving assignments related to electronics background. I m a VLSI expert
- Engineering
- Electrical Engineering
- Electronics
- Technology
- Robotics
Lesson location
About Sujeet
I have more than 15 years of teaching experience for Engineering students (Electronics Engineering) in Premier institutions like IIT, NIT and Gate Academy. I supervised more than 1000 hardware projects and also taken lab sessions on VLSI design EDA tools like Cadence, Mentor, Synopsys, and Xilinx (FPGA boards like Spartan, NEXYS DDR4, ARTIX, BYSYS, ZYBO, VERTEX etc). Successfully delivered more than 500 online projects and more than 5000 assignments (Electronics and computer architecture) for students of online platforms like TeacherOn, Upwork, Fiverr, Chegg, freelancer, hello-tutor etc. EDA Tools- 1. Cadence- virtuoso, layout Xl, Encounter, spectre X, Genus, Innovus, ORcad, Pspice-A/D etc. 2. Mentor Graphics- ModelSim, QuestaSim, Eldo, Calibre etc. 3. Synopsys- Design compiler(DC), IC compiler etc, H-spice. 3. Xilinx- VIVADO, ISE 4. LTSPICE 5. LOGISIM 6. Proteus 7. Microwind Layout editor 8. Quartus II Simulator 9. Incisive Enterprise Simulator 10. Intel Quartus Prime 11. Tanner 12. Python 13. Embedded C 14. RISC-V ISA Assembly Language 15. MIPS ISA Assembly Language 16. H-spice And many more......... => Design and Simulation of 40 MHz Phase Locked Loop(PLL) using Cadence virtuoso. => Design and Simulation of 1 GHz Phase Locked Loop(PLL) using Cadence virtuoso. => Design and Simulation of 2.4 GHz Phase Locked Loop(PLL) using Cadence virtuoso. => Fabricated a silicon chip of Phase Locked Loop(PLL) on 180 nm CMOS Technology. => Simulation and FPGA Prototype of 32-bit MIPS-based Processor Architecture. => Simulation and FPGA Prototype of 5-Stage pipelined 32-bit MIPS-based Processor Architecture. => Simulation and FPGA Prototype of 32bits RISC-V based Processor Architecture. => Simulation and FPGA Prototype of 5-Stage pipelined RV32I-based Processor Architecture. => RISC-V Based 32-Bit Processor on 180 nm CMOS Technology. => Simulation and FPGA Prototype of Stop Watch using Verilog. => Simulation and FPGA Prototype of Object-locator using Verilog. => 10 times GATE ECE qualified. => Best Rank-249 in 2014. Expert in :- => FPGA board (spartan series, Vertex Series, Zybo board, Nexys DDR, Artix, BYSYS, the Boolean Board, Pynq etc) projects => Lt-spice simulation => Logisim Tool for Digital architecture verification and analysis => Cadence Virtuoso, Layout Editor, Layout Xl, GXL, Spectre => Mentor Graphics - Eldo, Calibre, Design Architect (DA), Design Viewpoint Editor (DVE), ICStation, Accusim => Verilog HDL using XILINX Vivado and ISE, Modelsim => VHDL using XILINX Vivado and ISE, Modelsim => Arduino Projects using UNO, Mega and many boards => RTL simulations and synthesis using XILINX Vivado and ISE, Modelsim => Any subject assignments related to GATE electronics and communication syllabus. I am very interested in educating people through my skills and practical examples. To enhance my skills, I constantly upgrade myself through higher education and doing technical projects. If you want to see the problem differently, I can help you. Problem understanding is a skill that needs dedication to develop, so the solution to any problem has many ways. I am doing research at IIT and learning new things daily. If you solve a question a 2nd time, it will give you a different understanding. I am here to help, so you can join me if you want to see the problem from a unique perspective.
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About the lesson
- Primary
- Secondary
- SPM
- +5
levels :
Primary
Secondary
SPM
Form 6
STPM
Adult education
Masters
Doctorate
- English
All languages in which the lesson is available :
English
TOPICS COVERED:
SYSTEM DESIGN USING VERILOG HDL (9)
Hardware Modeling with Verilog HDL – Logic System, Data Types and Operators for Modeling in
Verilog HDL - Behavioral Descriptions in Verilog HDL – HDL Based Synthesis – Synthesis of Finite
State Machines – Structural modeling – Compilation and Simulation of Verilog code –Test bench -
Realization of combinational and sequential circuits using Verilog HDL.
SYNCHRONOUS SEQUENTIAL CIRCUIT DESIGN (9)
Analysis of clocked synchronous sequential circuits and modeling - State diagram, state table, state
assignment and reduction - Design of synchronous sequential circuits - Design of Iterative circuits -
ASM chart and realization using ASM.
ASYNCHRONOUS SEQUENTIAL CIRCUIT DESIGN (9)
Analysis of asynchronous sequential circuit – flow table reduction – Races - state assignment-
transition table and problems in transition table- Design of asynchronous sequential circuit - Static,
dynamic and essential Hazards – Data synchronizers – Mixed operating mode asynchronous circuits.
FAULT DIAGNOSIS AND TESTABILITY ALGORITHMS (9)
Fault table method- Path sensitization method – Boolean difference method - D algorithm - Tolerance
techniques – The compact algorithm – Fault in PLA – Test generation - DFT schemes – Built in self
test.
SYNCHRONOUS DESIGN USING PROGRAMMABLE DEVICES (9)
Programming logic device families – Designing a synchronous sequential circuit using PLA/PAL –
Realization of finite state machine using PLD – FPGA – Xilinx FPGA-Xilinx 4000.
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Rates
Rate
- RM84
Pack rates
- 5h: RM420
- 10h: RM840
online
- RM84/h
free lessons
This first lesson is free to allow you to get to know your teacher so that they can best meet your needs.
- 1hr
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